1. Field of the Invention
The invention relates generally to the field of semiconductor design and layout and computer automated design (CAD) for semiconductors. More specifically, the invention provides a method for managing the configuration, design parameters, and functionality of an integrated circuit design in which custom instructions and other elements may be arbitrarily controlled by the designer.
2. Description of Related Technology
Several types of computer aided design (CAD) tools are available to design and fabricate integrated circuits (IC). Such computer-aided or automated IC design tools can include modules or programs addressing both the synthesis and optimization processes. Synthesis is generally defined as an automatic method of converting a higher level of abstraction to a lower level of abstraction, and can include any desired combination of synthesis techniques which occur at various levels of abstraction. So-called “behavioral synthesis” is a design tool wherein the behavior (e.g. inputs, outputs, and functionality) of a desired IC are entered into a computer program to design a device that exhibits the desired behavior. Such tools permit IC designers to produce increasingly complex and capable devices, sometimes having logic gate counts in the tens of millions, with few or no errors and in a much shorter time period than would be otherwise possible with manual design techniques such as hand layouts.
Examples of synthesis processes which involve different levels of abstraction include architectural level synthesis and logic level synthesis, both of which may be incorporated into the IC design process.
Architectural level synthesis is primarily concerned with the macroscopic structure of the circuit; it utilizes functional blocks (including information relating to their interconnections and internal functionality). Architectural level synthesis includes register transfer level (RTL) synthesis, which can have multi-bit components such as registers and operators.
Logic level synthesis, on the other hand, is concerned with gate level design. Logic level synthesis determines a microscopic structure of a circuit and transforms a logic model into an interconnection of instances of library cells. The result of the logic level synthesis is a netlist of logic devices and their interconnections. Logic-level synthesizers (so-called synthesis “engines”) are available from several commercial vendors.
The synthesis process generally begins with the designer compiling a set of IC specifications based on the desired functionality of the target device. These specifications are then encoded in a hardware description language (HDL) such as VHDL® (VHSIC hardware description language) available from IEEE of New York, N.Y., or Verilog® available from Cadence Design Systems, Inc. of Santa Clara, Calif. The specifications define an IC in terms of the desired inputs and outputs, as well as desired functionality such as available memory or clock speed. From the HDL, the designer then generates a “netlist” including a list of gates and their interconnections, which is descriptive of the circuitry of the desired IC. Ultimately, the design is compiled and masks fabricated for producing the physical IC. FIG. 1 illustrates a typical prior art IC design and fabrication approach.
Unfortunately, while well suited for simpler devices and single components, the aforementioned prior art approaches to automated IC design suffer several limitations, especially when applied to the design of more complex ICs such as CPU-based processors. These problems stem largely from the requirement that the instruction set be fixed prior to, and not modifiable during, the design and synthesis processes, thereby reducing the flexibility and capability afforded the designer both during and after the design process. These problems are highlighted by the practice of supplying predefined CPU designs to users desiring to integrate a processor into their systems Integrated Circuit design. Specifically, by not being able to consider certain instructions, functions, or components in the design during synthesis, the designer is required to attempt to “backfit” these elements to the design, which often times creates compatibility issues or other problems. This disability also effectively precludes optimization of the design for certain parameters (such as die size or clock speed) since the resulting design necessarily has a higher gate count, and does not have the benefit of customized instructions specific to the desired architecture and functionality. Furthermore, such prior art systems are incapable of automatically assembling a HDL model of the complete processor and simulating its operation, an approach which can greatly increase the efficiency and effectiveness of the design process.
Based on the foregoing, an improved method (and associated apparatus) is needed for managing the configuration, design parameters, and functionality of an integrated circuit design in which the instruction set can be interactively varied by the user. Specifically, such an improved method would permit the user to add or subtract existing instructions, as well as generate new instructions specifically adapted for use with the design, while retaining the ability to verify the accuracy and correctness of the VHDL model and the subsequent synthesized logic or layout. Additionally, the improved method would allow the user to generate descriptive models of the complete processor as opposed to just individual logic circuits or modules, thereby further enhancing the simulation and synthesis processes. Furthermore, the user could automatically or interactively select various design parameters (such as the existence of a memory interface or peripheral component) during the design and synthesis processes to preclude having to retrofit or modify the design at a later time. This latter ability would greatly enhance the integration of such components into the design, thereby effectively eliminating incompatibilities, and reducing the resulting IC to its smallest possible dimension, clock speed, and power consumption, with the least amount of effort and cost.